Physical Design Engineer
Core
End-to-end execution of physical design for large System-on-Chip (SOC) blocks, covering synthesis, place-and-route, and all signoff stages.
Role type
Senior IC Physical Design Engineer
Builds
Production silicon tape-outs of SOC blocks in advanced foundry process nodes
Domain
Semiconductor / VLSI Physical Design
Required skills
Synthesis, Floorplanning, Place and Route, Timing Signoff, Physical Verification, EMIR Signoff, Formal Equivalence, Low Power Verification, Clock Construction (CTS), RTL to GDS implementation, PPA trade-off analysis, Data-driven methodology optimization
Preferred skills
Experience with high-speed clock construction strategies, Low power design methodology, Cross-functional collaboration
Technologies
Advanced foundry process nodes, SOC design flows, Physical Design tools
Responsibilities
Drive end-to-end execution from synthesis through place-and-route ensuring completion of all signoff stages; Responsible for SOC clocks and driving high speed clock construction and CTS; Own complete PD execution of medium to large-size SOC block; Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues
Seniority
Senior, hands-on IC
