AMS SerDes Robustness Analysis Validation Architect
Core
Architect and execute margin-to-fail validation strategies for high-speed SerDes PHYs (PCIe, USB) to uncover design weaknesses and stress-to-fail conditions.
Role type
Senior IC Validation Architect (SerDes/Analog)
Builds
Next-generation SerDes IPs and system-level high-speed serial links
Domain
Semiconductor / High-Speed Analog & Mixed-Signal
Required skills
SerDes design and validation principles, SOC/system integration, margin-to-fail methodologies, stress-to-fail techniques, analog/mixed-signal design, signal integrity (SI), power integrity (PI), high-speed serial link protocols (PCIe, USB, Ethernet, DisplayPort), equalization techniques (CTLE, DFE, FFE), lab instrumentation (oscilloscopes, BERTs, protocol analyzers), Python/C++ programming, design-for-test (DFT), root-cause analysis, silicon behavior analysis
Preferred skills
PhD in Electrical Engineering, silicon/system-level debug experience, validation automation, fault injection, internal monitors, behavioral hooks, multi-lane PHY validation, adaptive EQ, clocking and CDR paths, production and characterization flows, test coverage optimization
Technologies
PCIe, USB, Ethernet, DisplayPort, CTLE, DFE, FFE, Python, C/C++, Oscilloscopes, BERTs, Protocol Analyzers
Responsibilities
Define and architect margin-to-fail validation strategies; Develop and implement stress-to-fail methodologies; Collaborate with design teams to define coverage priorities and build DFT insertion; Lead hands-on lab experiments to validate assumptions and isolate issues; Partner with validation team to balance test coverage and execution time; Analyze silicon behaviors across builds and revisions; Provide post-silicon feedback to improve architectural decisions; Guide junior validation engineers and contribute to internal standard processes
Seniority
Senior, hands-on IC