Validation Engineer, Senior
Core
Define test plans, develop test methodologies, automate test equipment, characterize analog blocks, and perform PHY/Link Layer/Protocol compliance testing for high-performance ASICs.
Role type
Senior IC validation engineer (ASIC/SerDes)
Builds
High performance, high quality, low power world class products (ASICs/SoCs)
Domain
Semiconductors / Hardware Validation
Required skills
ASIC design/verification/validation, SerDes architecture (NRZ, PAM4), Python/Perl/C/C++ scripting, test instrument automation (Scope, BERT, Logic Analyzer), signal integrity analysis, PCIe/Ethernet protocol knowledge, PCB design
Preferred skills
MAC/PCS design blocks, optical and die2die validation, Mango Database/JavaScript for data analysis, Mango Database, HTML, JavaScript for data post processing and analysis
Technologies
PCIe (Gen1-Gen7), IEEE 100G CK, OIF 100G CEI, UCIe, SIGTEST, SEASIM, COM, Python, Perl, Matlab, C/C++, Scope, BERT, Logic Analyzer, VNA, Power Supplies, Multimeters
Responsibilities
Characterize analog blocks and perform PHY/Link Layer/Protocol compliance against various industry standards; Bring up silicon, debug issues, present test results, and generate validation reports; Define test plans and develop test methodologies for various tests; Develop and standardize test scripts for various tests and automate test equipment; Determine equipment and accessories needs for various tests; Study signal integrity and power integrity for evaluation boards and for silicon
Seniority
Senior, hands-on IC
