Analog Design Engineer - SERDES
Core
Design high-performance, high-speed AMS circuits for SerDes PHY components including Rx, CDR, Tx, bias generators, and clock distribution to achieve best-in-class PPA.
Role type
Senior IC Analog Designer (SerDes PHY)
Builds
High-speed serial link IP blocks for Apple products
Domain
Consumer electronics, high-speed analog mixed-signal
Required skills
Analog mixed-signal circuit design, high-speed serial link design, transistor-level implementation, behavioral modelling, mask design, SOC IP delivery, FinFet technology, AMS IC development lifecycle, layout supervision, bench evaluation, correlation, characterization, timing closure tools, high-speed SerDes protocols, scripting and automation
Preferred skills
PhD or Master's in Electrical Engineering, lab testing of high-speed serial I/O, debug and data analysis techniques, knowledge of PCIe/USB/DP/MPHY protocols
Technologies
SystemVerilog, Matlab, Python, VerilogAMS, Nanotime, Primetime
Responsibilities
Evaluate circuit topologies for specific product requirements, create block-level specifications, execute transistor-level implementation, drive mask design, interact with cross-functional teams (architecture, SIPI, packaging, board design, DFT, ESD), communicate progress and discuss new ideas with peers/management
Seniority
Senior, hands-on IC