Silicon Validation Engineer
Core
Lab characterization and validation of analog & mixed signal embedded circuits, specifically high-speed SerDes blocks, for mobile SoCs.
Role type
Senior IC silicon validation engineer (SerDes)
Builds
High-speed mobile SoCs
Domain
Consumer electronics / High-speed serial interfaces
Required skills
SerDes architecture (NRZ, PAM), CTLE, DFE, FFE, CDR, PLLs, signal integrity analysis, high-speed protocols (USB, PCIe, DP), test and measurement equipment (oscilloscopes, BERTs), PVT variation analysis, debugging, Python programming
Preferred skills
MSEE degree, extensive SerDes lab experience
Technologies
SerDes, USB, PCIe, DisplayPort, Python, Oscilloscopes, BERTs
Responsibilities
Lead efforts to bring up, validate, and characterize high-speed SerDes blocks. Analyze and debug critical SerDes components (CTLE, DFE, FFE, CDR, PLLs). Use high-speed test and measurement equipment to evaluate SerDes performance. Implement and assess SerDes adaptation techniques to improve signal integrity. Conduct detailed signal integrity analysis for high-speed data transmission. Develop and execute test methodologies to determine operating margins across PVT variations. Collaborate with ATE and Product Engineering teams.
Seniority
Senior, hands-on IC