RFIC Layout Engineer
Core
Designing and verifying transistor-level layouts for RF and analog circuit blocks in wireless SoCs to enable high-volume production of energy-efficient radios.
Role type
RFIC Layout Engineer
Builds
Wireless SoC radio blocks (LNAs, mixers, PLLs, modulators, PAs, ADC/DACs, filters, references)
Domain
Wireless communications, RF/analog IC design, advanced CMOS
Required skills
FinFet layout, transistor-level layout, block floorplanning, DRC/LVS/DFM verification, power/gnd routing, electromigration analysis, signal coupling analysis, differential/IQ matching, CADENCE tools, CALIBRE DRC/ERC/LVS interpretation, scripting (PERL/SKILL)
Preferred skills
Custom RF/analog layout for transceivers, deep sub-micron CMOS knowledge, device matching techniques, parasitic minimization, RF shielding, high-frequency routing, advanced process effects (LOD, WPE), guard rings, DNW, PN junctions
Technologies
FinFet, CMOS, CADENCE, CALIBRE, PERL, SKILL
Responsibilities
Create detailed transistor-level layouts for RF/analog blocks; Perform block-level layout verification including extraction, DRC, LVS, and DFM; Collaborate on block-level floorplanning; Review layouts for routing, matching, and coupling issues
Seniority
Mid-level, hands-on IC
