ESD Engineer
Core
Define ESD methodology and design protection circuits to ensure silicon ICs are immune to ESD and latch-up events while meeting manufacturing requirements.
Role type
Senior IC ESD Engineer
Builds
High-quality on-chip IPs immune to ESD/EOS and latchup events
Domain
Semiconductor / Silicon IC Design
Required skills
ESD circuit design, transistor device characteristics, ESD test models (HBM, CDM, MM, IEC-61000-4-2), EDA tools (Virtuoso, Calibre, Allegro), ESD checking tools (PERC, Pathfinder), Si process knowledge for high voltage/RF/ASICs, ESD/LUP test equipment operation
Preferred skills
MS degree, 8+ years experience, advanced ASIC process knowledge
Technologies
Virtuoso, Calibre, Allegro, PERC, Pathfinder
Responsibilities
Define ESD methodology and specify chip/IP level requirements; Design ESD protection devices and circuits; Develop test structures for Si characterization; Create design rules based on characterization data; Collaborate with foundries on library and rule development; Maintain ESD device library; Generate/review testing plans; Manage sign-off reviews; Drive ESD/LUP debug activities
Seniority
Senior, hands-on IC
