Wireless Design Verification Engineer
Core
Senior IC verification engineer developing sophisticated testbenches and verification strategies for next-gen WiFi SoCs to ensure first-time-right silicon success.
Role type
Senior IC wireless design verification engineer
Builds
Multi-gigabit wireless SoCs for Apple products
Domain
Consumer electronics / Wireless connectivity
Required skills
SystemVerilog, UVM, constrained random testing, functional coverage, assertion-based verification, ASIC verification flows, testbench architecture, verification planning, coverage-driven methodologies, simulation bring-up
Preferred skills
Python scripting, DPI integration, bus functional models (BFMs), transaction-level modeling, verification IP development, formal verification, low-power methodologies, large-scale regression infrastructure
Technologies
SystemVerilog, UVM, Python
Responsibilities
Lead subsystem-level verification from test planning through feature closure; Architect sophisticated UVM testbench environments and reusable verification IP; Develop constrained random scenarios for complex protocol and multi-domain behaviors; Drive coverage-driven methodologies and metric analysis frameworks
Seniority
Senior, hands-on IC
