RTL Design Engineer
Core
Design and verify mixed-signal digital blocks and signal processing pipelines for Apple silicon, translating DSP algorithms into efficient RTL.
Role type
Senior IC RTL Design Engineer (mixed-signal/DSP)
Builds
High-performance mixed-signal and analog IPs integrated into high-speed digital circuits
Domain
Semiconductor / Mixed-signal silicon design
Deliverable
production ML models | product features
Required skills
RTL coding (Verilog/SystemVerilog), DSP algorithm implementation, design verification (assertions, testbenches), lab bring-up and characterization, hardware-software co-design
Preferred skills
Front-end tools (simulators, linters, CDC checkers), synthesis and static timing analysis, DFT, formal verification, low-power design, scripting (Perl/Python), GenAI proficiency for hardware design
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