PHY Design Verification Engineer
Core
Pre-silicon RTL verification of wireless PHY and its interfaces within a wireless communication SoC.
Role type
Senior IC design verification engineer (wireless PHY)
Builds
Wireless silicon SoCs for consumer devices
Domain
Wireless communications, VLSI, ASIC design
Deliverable
production ML models
Required skills
SystemVerilog, UVM, constrained random testing, coverage modeling, Python scripting, Palladium/FPGA validation, AI/ML for design analysis
Preferred skills
Wireless protocols (Bluetooth, UWB, WLAN, Zigbee), Matlab/C reference models, ASIC verification flows
Responsibilities
Create verification plans from specifications to achieve coverage targets; Build reusable block/subsystem test benches with reference models; Develop and execute directed and constrained random tests; Debug failures and manage bug tracking; Analyze coverage models and add test cases; Support validation using Palladium and/or FPGA; Improve DV methodology and flow.
Seniority
Senior, hands-on IC
