PHY Design Verification Engineer
Core
Pre-silicon RTL verification of wireless PHY and its interfaces within a wireless communication SoC.
Role type
PHY Design Verification Engineer
Builds
Reusable testbenches and verification environments for wireless silicon
Domain
Wireless silicon / RF/Analog / VLSI
Required skills
SystemVerilog, UVM, constrained random testing, coverage modeling, Python scripting, Palladium/FPGA validation, wireless protocol knowledge (Bluetooth, UWB, WLAN, Zigbee), AI/ML for design analysis
Preferred skills
MSEE degree, 2+ years wireless verification experience, Matlab/C reference modeling, shell scripting, AI technologies in data mining
Technologies
SystemVerilog, UVM, Palladium, FPGA, Python, Matlab, C, Perl
Responsibilities
Create verification plans from specifications to achieve coverage targets; Build block/subsystem level test benches with reference models; Develop and execute directed and constrained random tests; Debug failures and manage bug tracking; Create and analyze coverage models; Support PHY subsystem validation using Palladium and/or FPGA; Improve DV methodology and flow
Seniority
Mid-level IC Engineer
