Experienced ASIC Analog Layout Engineer (m/f/d)
Core
Top-level integration of analog and mixed-signal ICs, driving layout development for robust, DRC-compliant designs with optimal area utilization.
Role type
Senior ASIC Analog Layout Engineer
Builds
Analog and mixed-signal semiconductor chips for internal strategic demands
Domain
Semiconductor / Automotive
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
top-level layout integration, floorplanning, padframe design, parasitic extraction, DRC/LVS compliance, analog circuit design knowledge, BCD technology expertise (65nm-180nm), layout tool proficiency
Preferred skills
German language skills
Technologies
BCD technologies (65nm to 180nm), layout tools for design, DRC, LVS, and extraction
Responsibilities
Define toplevel floorplan, padframe design and bonding diagrams; coordinate with other layouters and drive floorplans; generate and integrate analog layouts at block and chip level; perform pin placement and layout optimization; support tape-out activities; collaborate to meet speed, area, power, DFM, ESD, and EMC requirements
Seniority
Senior, hands-on IC
