ASIC Analog Layout Engineer (m/f/d) - REF5390S
Core
Top-level integration of analog and mixed-signal ICs, driving layout development for robust, DRC-compliant designs with optimal area utilization.
Role type
Senior IC ASIC Analog Layout Engineer
Builds
Analog and mixed-signal silicon chips
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
top-level layout integration, floorplanning, padframe design, bonding diagram creation, block-level analog layout, pin placement, parasitic extraction, layout optimization, DRC/LVS compliance, tape-out support, BCD technology expertise (65nm-180nm), deep submicron effects understanding, analog circuit design knowledge
Preferred skills
German language proficiency
Technologies
Layout tools for design, DRC, LVS, and extraction
Responsibilities
Define toplevel floorplan and padframe design, coordinate with other layouters for chip top-level floorplans, generate and integrate analog layouts at block and chip level, perform pin placement and parasitic extraction, ensure compliance with DRC, LVS, and support tape-out activities, collaborate with design engineers to meet speed, area, power, DFM, ESD, and EMC requirements
Seniority
Senior, hands-on IC
