Logic Design Engineer
Core
Develop and integrate RTL functional blocks for SOC clock controllers, ensuring timing closure, low power intent, and functional correctness.
Role type
Senior IC logic design engineer (clock controller IP)
Builds
SOC clock controller IP blocks
Domain
Semiconductor / Digital Logic Design
Required skills
RTL coding (Verilog/System Verilog), Timing closure, Low Power Analysis (UPF), Clock crossing design, Synthesis, CDC analysis, Scripting/Automation, Interface protocols (ARM)
Preferred skills
Formal Equivalence Verification, Power Analysis
Technologies
VCLP, Verilog simulators, Connectivity tools, low power static checkers, linting
Responsibilities
Develop and integrate RTL for SOC clock controllers; Perform design quality checks (Timing, Lint, CDC, Synthesis, Low Power); Interface with verification, physical design, and DFT teams; Write basic tests and debug features at IP and SoC levels; Automate tasks using scripting.
Seniority
Mid-Senior, hands-on IC
