Principal Physical Design Engineer
Core
Lead end-to-end physical design flow from synthesis through place-and-route for SOC blocks, ensuring signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Role type
Principal Physical Design Engineer (IC)
Builds
SOC blocks and subsystems for advanced foundry process nodes
Domain
Semiconductor / Physical Design / VLSI
Required skills
End-to-end physical design flow ownership, Synthesis, Floorplanning, Place and Route, Timing signoff, Physical verification, EMIR signoff, Formal equivalence, Low-power verification, Clock construction and CTS, Methodology exploration, PPA trade-off analysis, Data-driven optimization, Cross-functional collaboration
Preferred skills
Advanced foundry process node experience, Low-power design methodology, High-speed design clock strategies, Medium to large-size SOC block execution
Technologies
Synthesis tools, Place-and-route tools, Verification tools, EMIR tools, Formal equivalence tools, Clock construction tools
Responsibilities
Lead and execute end-to-end PD flow from synthesis through place-and-route, Drive methodology exploration to optimize SOC blocks, Coordinate with CAD, RTL/Design, DFT, Architecture, Power & Performance, and Technology teams, Own complete PD execution of medium to large-size SOC blocks, Partner with PD flow/CAD and methodology teams to fix TFM issues
Seniority
Principal, hands-on IC with strategic influence
