Senior SOC Integration Engineer
Core
Own SOC implementation and integration strategies, ensuring RTL quality, integrating functional blocks into the SOC FPGA, and leading gate-level simulation.
Role type
Senior SOC Integration Engineer
Builds
ASIC IPs, sub-systems, and top-level SOC RTL
Domain
Semiconductor / Computer Architecture / Digital Design
Required skills
SOC Integration, Computer Architecture, Digital Design, IP and SOC development, Verilog/System Verilog, RTL tools and flows, high performance and low power design, ASIC delivery, gate-level simulation, clock/reset design, Python/Perl/Tcl scripting, design for testability and debug
Preferred skills
PCIe, Fabric, Security, CPU, Coherence, high speed interfaces/protocols
Technologies
Verilog, System Verilog, Python, Perl, Tcl, Lint, CDC, RDC, synthesis, timing analysis, power analysis, SCM, RTL partitioning
Responsibilities
Own SOC implementation and integration strategies; Work with SOC Integration and IP Design Engineers to ensure RTL quality and timeliness; Integrate various functional blocks into the SOC FPGA; Exercise functionality by writing basic tests and debug; Lead the gate-level simulation team; Perform design quality checks (Lint, CDC, RDC, Low Power Intent); Work with the verification team to ensure Design quality.
Seniority
Senior, hands-on IC
