Senior Physical Design Engineer
Core
Drive end-to-end execution from synthesis through place-and-route for large System-on-Chip (SOC) blocks, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Role type
Senior IC Physical Design Engineer
Builds
SOC blocks and production silicon tape-outs in advanced foundry process nodes
Domain
Semiconductor / Physical Design
Required skills
Synthesis, place-and-route, clock construction and CTS, physical verification, EMIR, formal equivalence, low-power design methodology, PPA trade-offs, RTL to GDS implementation, floorplanning, extraction, signoff
Preferred skills
Data-driven approach to influence tools and flows, cross-functional collaboration, problem-solving, data analysis
Technologies
Advanced foundry process nodes, SOC design tools, CAD tools
Responsibilities
Drive methodology exploration to optimize SOC blocks for clock construction; Coordinate with CAD, RTL/Design, DFT, Architecture, Power & Performance, and Technology teams; Own complete PD execution of medium to large-size SOC blocks; Partner with PD flow/CAD and methodology teams to flag and fix TFM issues
Seniority
Senior, hands-on IC
