Principal Design Verification Engineer - Formal
Core
Lead formal verification of fabric interconnect architectures, IPs, subsystems, and reusable components from planning through signoff.
Role type
Principal Design Verification Engineer (Formal)
Builds
Fabric Interconnect architectures, IPs, subsystems, and reusable components
Domain
Semiconductor hardware design and verification
Required skills
Formal verification methodologies, System Verilog, UVM, assertions, coverage-driven verification, Python scripting, AI-assisted verification tools, root-cause analysis, automation, mentorship
Preferred skills
Expertise in Fabric Interconnects, coherency, CHI, AMBA, PCIe, CXL, protocol bridges, virtualization, security, or memory subsystems
Technologies
System Verilog, UVM, Python
Responsibilities
Define formal verification strategies, methodologies, test plans, and signoff criteria; develop and enhance formal verification environments, assertions, and checkers; drive root-cause analysis and closure of complex design issues; improve verification productivity through automation and AI-assisted solutions; coach and mentor engineers in formal verification best practices
Seniority
Principal, hands-on IC with strategy & mentorship
