Design Verification Engineer
Core
Develop pre-silicon verification and post-silicon validation for custom silicon components, including writing constrained random stimulus, scoreboards, checkers, and assertions.
Role type
Design Verification Engineer (Pre-silicon & Post-silicon)
Builds
Custom silicon components, verification IP (VIP), and UVM components
Domain
Semiconductor / Hardware Design / System on Chip (SoC)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Constrained random stimulus, scoreboards, checkers, assertions, Verification IP (VIP), Universal Verification Methodology (UVM), functional coverage, drive coverage, SystemVerilog, C/C++, Python/Ruby/Perl scripting, test plan development, testbench creation, stimulus generation, coverage-based verification, debugging, formal verification, automation
Preferred skills
Experience with Coherency, Caches, Fabrics, DDR controllers, PCIe, CXL, AXI/CHI protocol bridges, full product cycle from definition to silicon, IP/block/subsystem level test plans, SVTB, formal verification integration
Technologies
SystemVerilog, UVM, OVM, Python, Ruby, Perl, C, C++, SVTB, Formal Verification
Responsibilities
Write constrained random stimulus, scoreboards, checkers, and assertions; Develop Verification IP (VIP) and UVM components; Define and implement functional and drive coverage closure; Collaborate with Architecture, Design, Firmware/Software, and vendor teams; Develop scripts for verification and validation infrastructure; Debug failures and achieve coverage signoff
Seniority
Mid-level to Senior, hands-on IC
