Principal Silicon Design Verification Manager
Core
Lead and mentor a silicon engineering team while owning the verification strategy for complex silicon subsystems from planning through closure.
Role type
Principal Silicon Design Verification Manager
Builds
High-quality silicon subsystems including subsystem integration and third-party IP integration
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Note: The role builds silicon subsystems/IPs, which maps to 'product features' in the context of hardware, but the strict list options are tricky. Let's re-evaluate based on the prompt's specific list: 'production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work'. Hardware IP is best fit for 'product features' or 'infrastructure'. Given the context of 'silicon subsystems', 'product features' is the closest semantic match for the deliverable of the team's work, though 'infrastructure' fits the verification environment. However, the primary output is the silicon subsystem. I will select 'product features' as it represents the hardware deliverable.)
Required skills
SystemVerilog, UVM, constrained-random verification, coverage-driven verification, Python automation, formal verification, low-power verification, performance verification, hardware security (crypto engines, secure boot, trusted execution), emulation (Palladium), testbench architecture, debug, coverage analysis, verification closure
Preferred skills
AI-assisted verification techniques, physical design considerations, synthesis, timing closure
Technologies
SystemVerilog, UVM, Python, Linux, Git, Palladium
Responsibilities
Lead and mentor a team of design verification, silicon design, and physical design engineers; Own and drive verification strategy for complex silicon subsystems; Provide hands-on technical contribution in verification planning, testbench architecture, and debug; Build and promote modern verification workflows including AI-assisted techniques; Collaborate with architecture, design, system engineering, firmware, and physical design partners
Seniority
Principal, hands-on IC with people management
