Senior Test Engineer
Core
Senior Test Engineer responsible for scan (structural) test, silicon bring-up, validation, and manufacturing readiness for semiconductor ICs.
Role type
Senior IC Test Engineer (Scan/Structural)
Builds
Semiconductor chips (SoCs) for high-performance computing, AI, GPUs, and telecom
Domain
Semiconductor / Integrated Circuit Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan test methodologies, ATPG, DFT (scan architecture, fault models), ATE platform debugging, yield analysis, failure analysis, test plan execution, cross-functional collaboration, Linux environments, probability/statistics/DOE concepts
Preferred skills
Mixed-signal IP test development, simulation/emulation, advanced-node design experience
Technologies
Advantest 93K, JTAG, boundary scan, at-speed testing, scan diagnosis tools
Responsibilities
Execute test plans and methodologies for scan test readiness and coverage closure; Contribute to ATE test program development including pattern integration and bring-up; Perform silicon characterization, debug, and yield analysis for logic defects; Utilize scan diagnosis tools for failure analysis and defect location identification; Collaborate with design, DFT, and manufacturing teams for issue resolution; Support simulation, emulation, and pattern verification for scan test validation
Seniority
Senior, hands-on IC development and test engineering
