Senior Design Verification Engineer
Core
Build, validate, and automate emulation models; develop complex verification environments and test suites for pre- and post-silicon validation of IP/Subsystem/SoC-level designs.
Role type
Senior Design Verification Engineer (SoC/Chip)
Builds
Production silicon IP, subsystems, and SoC designs
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (verification environments, test suites, emulation models)
Required skills
System Verilog, UVM, constrained random testing, assertions, functional coverage modeling, emulation (Zebu/Palladium), FPGA, Verilog, C/C++, Python, Ruby, Perl, hardware architecture, firmware boot flow, synthesizable code
Preferred skills
CPU or Graphics core verification, hardware emulation, cross-functional collaboration across sites
Technologies
Zebu, Palladium, System Verilog, UVM, Python, Ruby, Perl, Makefiles
Responsibilities
Develop complex verification environments and test suites; create and drive comprehensive test plans; triage and debug failures in testbenches, simulations, and emulation environments; develop automation scripts for scalable verification flows; collaborate with architects to define verification strategies and plans.
Seniority
Senior, hands-on IC
