Principal Circuit Design Engineer
Core
Develop Memory SRAM and Register file solutions to address difficult PPA challenges for SoC designers.
Role type
Principal Circuit Design Engineer (Memory IP)
Builds
Memory SRAM and Register file IP for advanced process technology testchips and SoCs
Domain
Semiconductor / VLSI Design / Memory
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SRAM and Register file design, Statistical analysis, Timing/power/EMIR characterization, IP development, Post-silicon characterization, Scripting automation, Advanced process technology knowledge, DTCO, Layout design guidance, Yield and reliability analysis
Preferred skills
SRAM write and read assist techniques, AI for circuit design tasks, Technical guidance to other engineers, Multitasking across SoC programs, PERL/Python/TCL scripting
Technologies
PERL, Python, TCL
Responsibilities
Collaborate with SoC designers to develop Memory SRAM and Register file solutions, Work with process technology teams to exploit advanced process DTCO knobs, Devise methodologies for statistical analysis and timing/power/EMIR characterization, Run quality assurance checks on IP collateral, Develop IP and post-silicon characterization plans, Develop scripting automation for flows
Seniority
Principal, hands-on IC with strategy & mentorship