Principal Memory Controller RTL Design Engineer
Core
Define and implement micro-architectural specifications for memory controllers in Verilog/System Verilog, optimizing for area, power, and performance within SoC environments.
Role type
Principal Memory Controller RTL Design Engineer
Builds
High-quality functional memory controller IP blocks integrated into System-on-Chip (SoC) designs.
Domain
Semiconductor hardware design, memory subsystems, SoC integration.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog/System Verilog, SoC integration, low power design, high-speed design, scripting (Perl/Tcl/Python), multi-bit error correction (Reed-Solomon), industry interface protocols (CHI, APB, AMBA), synthesis and static timing analysis (STA), linting and CDC/RDC checks.
Preferred skills
10+ years designing DDR4/DDR5 memory controllers, front-end tool proficiency, multi-bit error correction expertise.
Technologies
Verilog, System Verilog, DDR4, DDR5, CHI, APB, AMBA, Perl, Tcl, Python, Synthesis tools, STA tools.
Responsibilities
Define and implement micro-architectural specifications, refine implementations for area/power/performance, integrate functional IP into SoC, write basic tests for functionality, perform design quality checks (Lint, CDC/RDC, Low Power Intent, timing QoR), automate tasks using scripting and AI.
Seniority
Principal, hands-on IC with strategic oversight.
