VLSI Design Verification Masters Level Intern
Core
Develop SystemVerilog and UVM testbench components, constrained-random tests, and functional coverage for HPE Slingshot interconnect ASIC verification.
Role type
VLSI Design Verification Intern
Builds
Switch or NIC ASIC verification projects for HPC and AI systems
Domain
Semiconductor / High-Performance Computing / AI Infrastructure
Required skills
SystemVerilog, UVM, Digital Design, Computer Architecture, Object-Oriented Programming, Debugging, Functional Coverage Analysis
Preferred skills
Hardware Description Languages (Verilog/VHDL), Python/Perl/Tcl scripting, Linux development environments, Distributed team collaboration
Technologies
SystemVerilog, UVM, HPE Slingshot, Linux
Responsibilities
Develop testbench models, monitors, scoreboards, and checkers; Write constrained-random tests; Analyze functional coverage; Debug regression failures; Collaborate with ASIC designers and architects; Use scripting and AI-assisted tools for verification automation
Seniority
Intern
