Director, ASIC Design & Front-End Implementation
Core
Lead the ASIC Design and Front-End Implementation organization to deliver next-generation networking ASICs powering HPE Networking products.
Role type
Director, ASIC Design & Front-End Implementation
Builds
Networking ASICs for HPE Networking products
Domain
Semiconductor / Networking
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design, Verilog/SystemVerilog, microarchitecture development, synthesis, CDC, linting, timing closure, ASIC implementation flows, cross-functional leadership, program execution
Preferred skills
Networking ASICs, switching/routing architectures, packet processing, QoS, security, telemetry, AI networking solutions, silicon bring-up, validation, post-silicon debug, global distributed engineering leadership, methodology automation
Technologies
Verilog, SystemVerilog
Responsibilities
Lead RTL design and microarchitecture teams; Drive design execution from architecture through tapeout; Partner with Physical Design for implementation readiness; Collaborate across Architecture, Verification, Software, and Product teams; Manage schedules, dependencies, and risks for multiple ASIC programs; Lead engineering managers and senior technical contributors
Seniority
Director, hands-on IC leadership
