Senior Design Verification Engineer
Core
Develop and execute comprehensive verification strategies for complex digital designs using emulation-based platforms to ensure functional correctness and performance targets prior to silicon tape-out.
Role type
Senior IC design verification engineer (emulation-based)
Builds
Robust testbench environments, verification plans, and sign-off reports for IP-level and system-level designs
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification infrastructure & testbenches)
Required skills
SystemVerilog, UVM methodology, emulation-based verification, constrained-random verification, functional coverage, RTL design concepts, waveform analysis, assertion-based verification (SVA), scripting (Python/Perl/TCL)
Preferred skills
Networking protocols (Ethernet, PCIe, CXL), interface protocols (AXI, AHB, I2C), formal verification, FPGA prototyping, power-aware verification (UPF/CPF), SoC-level verification, processor architectures (ARM, RISC-V, x86), CI/CD frameworks
Technologies
Cadence Palladium, Synopsys ZeBu, Mentor Veloce, JasperGold, VC Formal
Responsibilities
Develop verification plans for IP and system-level designs; Build and maintain UVM/SystemVerilog testbenches; Run directed and constrained-random tests; Configure and run designs on emulation platforms; Debug complex design issues using waveform and log analysis; Drive coverage closure and generate sign-off reports; Support software/firmware teams with early bring-up activities; Improve verification processes and flows
Seniority
Senior, hands-on IC
