ASIC front-end Design Engineer
Core
Architecting and designing high-performance blocks for advanced networking ASICs to deliver maximum throughput and minimum power.
Role type
ASIC front-end design engineer
Builds
High-speed networking ASICs for large, complex systems
Domain
Networking hardware / ASIC design
Deliverable
production ML models | product features
Required skills
Verilog RTL coding, micro-architecture design, logic design, ASIC debugging, timing constraint analysis, high-speed serial interface design, multi-domain clock synchronization, memory subsystem design
Preferred skills
Synopsys Design Compiler, Verplex LEC, Spyglass, Ethernet protocol design, FCoE protocol design
Technologies
Verilog, Synopsys Design Compiler, Verplex LEC, Spyglass
Responsibilities
Define and architect high-performance blocks for networking ASICs; Perform micro-architecture and logic design; Collaborate with verification teams on test plans and debugging; Collaborate with physical design teams on timing constraints and fixes
Seniority
Mid-level IC engineer
