Yield Enhancement Engineer, Texas Institute for Electronics
Core
Drive yield improvement, defect reduction, and process optimization for advanced packaging technologies in high-volume semiconductor manufacturing.
Role type
Yield Enhancement Engineer (Semiconductor Process Integration)
Builds
Advanced packaging products and manufacturing processes for national security and domestic economic growth.
Domain
Semiconductor manufacturing / Advanced packaging
Required skills
Statistical data analysis (JMP, Minitab, Python, Excel), DOE, SPC, Cp/Cpk, yield analysis, defect reduction, root cause analysis, process integration, failure analysis, cross-functional collaboration
Preferred skills
Advanced packaging (hybrid bonding, TSV, Cu damascene), reliability failure mechanisms, automation/data visualization, AI/ML-based yield analytics
Technologies
JMP, Minitab, Python, Excel
Responsibilities
Analyze electrical, inline, defectivity, and reliability data to identify yield loss mechanisms; Develop and execute yield improvement plans for NPI and high-volume manufacturing; Perform process integration studies across lithography, etch, deposition, CMP, plating, cleaning, and metrology; Correlate process parameters with yield, reliability, and device performance metrics; Drive root cause analysis using DOE, SPC, Pareto analysis, FMEA, and statistical methodologies; Support technology transfer from development to manufacturing; Work closely with process, equipment, quality, product, reliability, and customer teams to resolve technical issues; Monitor excursion trends and establish preventive actions; Define process control strategies, specifications, and yield monitoring methodologies; Participate in failure analysis reviews and develop containment/corrective action plans; Support customer qualification activities and technical discussions; Generate technical reports, presentations, and documentation for management and customers
Seniority
Mid-level IC (3+ years experience)