ASIC Design Engineer, ML Acceleration Team
Core
Design and implement high-performance, area-efficient, and power-efficient RTL designs for custom machine learning inference server architectures.
Role type
Senior IC ASIC Design Engineer (ML Acceleration)
Builds
Custom SoCs and hardware accelerators for AWS machine learning servers (e.g., Inferentia)
Domain
Cloud computing / Machine Learning Hardware / ASIC Design
Deliverable
production ML models
Required skills
SystemVerilog, RTL design, microarchitecture design, formal verification, debugging, validation, Python/Perl scripting, ARM/DSP instruction set architectures, RF standards knowledge
Preferred skills
Masters degree in Electrical/Communications Engineering, high-performance/power-efficient design experience, interconnects/DMAs/memory subsystems knowledge, patent generation
Technologies
SystemVerilog, Python, Perl, ARM, AWS Cloud, Machine Learning
Responsibilities
Analyze designs and microarchitectures to balance features, power, performance, and area; write SystemVerilog RTL and deliver synthesis-ready, timing-clean designs; run lint and clock-domain-crossing quality checks; collaborate with architects, verification, and validation teams; optimize hardware for data center ML inference servers
