ASIC Engineer, Annapurna Labs
Core
Design and optimize high-performance, area- and power-efficient RTL designs for cloud-scale machine learning inference servers.
Role type
Senior IC ASIC Engineer (Hardware Design)
Builds
Custom machine learning inference servers (e.g., AWS Inferentia) for AWS data centers
Domain
Semiconductor hardware design, cloud infrastructure, machine learning acceleration
Deliverable
production ML models (hardware implementation)
Required skills
RTL design, SystemVerilog, microarchitecture design, formal verification, debugging architecture/algorithms, validation at multiple levels (IP to SoC), ARM/DSP instruction set architectures
Preferred skills
Masters/PhD in EE, formal verification methods, RF standards (cellular, WiMAX, 802.11ad, microwave backhaul, DVB), Python/Perl scripting, AWS Cloud
Technologies
SystemVerilog, Python, Perl, ARM, AWS Cloud
Responsibilities
Develop and implement high-performance RTL designs; analyze designs and microarchitectures to balance functionality, power, performance, and area; create microarchitectures and deliver synthesis- and timing-clean designs; run lint and clock-domain crossing checks; partner with architects, verification, and validation teams
