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Engineering Lead

New Cairo, EGY, Egypt💼 Full-time💰 $44,000–$44,000🗓 2026-07-22

Core

Lead system-level validation and verification for high-speed interconnect solutions (PCIe, CXL, NVMe, UCIe) across emulation and FPGA prototyping platforms.

Role type

Sr. Staff Pre-Silicon Validation/Verification Lead

Builds

End-to-end pre-silicon verification strategies, scalable validation environments, and CI/CD pipelines for HW/SW co-verification.

Domain

Semiconductor design, Electronic Design Automation (EDA), high-speed interconnect protocols

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

System-level testing and verification, interconnect protocols (PCIe, CXL, NVMe, AXI, UCIe), hardware-assisted verification platforms (Veloce, Palladium, ZeBu), FPGA prototyping, SystemVerilog, SystemC, HW/SW co-verification, C/C++, bare-metal testing, Linux drivers, CPU architectures, memory hierarchies, IOMMU, cache coherency, virtualization, debugging (RTL, protocol, system-level), CI/CD pipelines, test automation (Python, Bash), verification strategy definition, cross-functional technical leadership

Preferred skills

null

Technologies

Veloce, Palladium, ZeBu, SystemC, UVM, SystemVerilog, C, C++, Python, Bash, PCIe, CXL, NVMe, AXI, UCIe

Responsibilities

Lead testing and verification activities for high-speed interconnect protocols; Architect and drive end-to-end pre-silicon verification strategies; Build and scale verification environments integrating transactors, RTL monitors, BFMs, and software stacks; Drive system-level validation of performance, interoperability, and scalability; Own and evolve regression strategy including coverage tracking and failure triage; Design and maintain scalable CI/CD pipelines and validation infrastructure; Ensure QA readiness through structured validation workflows; Lead deep-dive debugging and root-cause analysis of complex protocol failures; Collaborate with cross-functional teams to ensure feature readiness; Mentor engineers and conduct design and test plan reviews.

Seniority

Sr. Staff, hands-on IC with leadership

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