Lead Member Technical Staff
Core
Lead the design and development of next-generation RTL-to-GDSII solutions, focusing on low power implementation and optimization from RTL through Place and Route.
Role type
Senior IC technical lead (EDA software)
Builds
Core modules of RTL-to-GDSII design flow and Place and Route components
Domain
Electronic Design Automation (EDA) / Chip design
Deliverable
production ML models | product features
Required skills
C/C++ proficiency, algorithm design, data structures, software architecture, team mentoring, RTL/gate-level netlist understanding
Preferred skills
Low power design methodologies (UPF), Verilog/VHDL, Python/Tcl scripting, Place and Route algorithms
Technologies
C, C++, Python, Tcl, Verilog, VHDL, UPF
Responsibilities
Design and develop core modules for RTL-to-GDSII solution; Lead architecture and implementation of Place and Route components; Mentor and guide software engineers; Develop and optimize algorithms and data structures; Collaborate with cross-functional teams to define technical requirements; Drive code quality and technical standards
Seniority
Senior, hands-on IC with leadership