Software R&D Engineer, RTL Optimization Tools
Core
Develop highly optimized internal EDA tools for large-scale RTL quality, timing, and power optimization by fusing parallel computing, machine learning, and novel algorithms.
Role type
Senior IC CAD Software Engineer (RTL Optimization)
Builds
Internal EDA tools for hardware design productivity
Domain
Semiconductor / VLSI / EDA
Deliverable
production ML models | product features
Required skills
C++ algorithm development, graph traversal, pattern matching, RTL design (Verilog/SystemVerilog), logic synthesis, static timing analysis, machine learning (LLMs, GNNs, Reinforcement Learning), high-performance software design
Preferred skills
SOC/IP integration, DFT, clock distribution, power gating, Verific, Espresso, SAT solvers, combinatorial optimization
Technologies
C++, Verilog, SystemVerilog, LLMs, GNNs, GANs, Verific, Espresso
Responsibilities
Invent methods for parallel RTL traversal and analysis; devise strategies for analyzing RTL impact on latency and power; explore ML techniques for RTL modification; develop high-performance algorithms for logic synthesis and technology mapping; drive the roadmap for increasing hardware design productivity
Seniority
Senior, hands-on IC