Senior Member Technical Staff
Core
Design and development of RTL synthesis technology, logic optimizations, and low power synthesis for complex digital IC designs.
Role type
Senior IC software engineer (RTL synthesis)
Builds
Next generation RTL-to-GDSII solution
Domain
Electronic Design Automation (EDA) / Semiconductor
Deliverable
production ML models | product features
Required skills
C++, algorithm and data structures, RTL synthesis tool development, logic optimizations, low power synthesis
Preferred skills
System Verilog, VHDL, UPF, DFT, formal verification, Dynamic Power, parallel algorithms, Python, Tcl
Technologies
C++, System Verilog, VHDL, UPF, Python, Tcl
Responsibilities
Drive design and development of RTL synthesis technology and logic optimizations; Guide and lead others toward successful project completion; Collaborate with a team of experts
Seniority
Senior, hands-on IC
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