Lead Semiconductor Packaging Engineer - 843
Core
Develop innovative and reliable packaging schemes for highly scaled ion traps in quantum computers, including tiling large assemblies of ion trap, electrical, and optical chips.
Role type
Lead Semiconductor Packaging Engineer
Builds
Packaging solutions for large-format ion trap chips with high I/O signal count and density
Domain
Quantum computing / Semiconductor packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Advanced semiconductor packaging development, Large-area multi-chip packaging, Heterogeneous integration, 2.5-3D packaging techniques, High-density I/O technologies, Photonic packaging, Fiber-to-chip coupling, Optical chip-to-optical chip coupling, Cross-functional team leadership, Vendor management, System requirements alignment
Preferred skills
PhD in Physics or Engineering, Innovation and IP development track record
Technologies
Ion trap chips, Electrical chips, Optical chips, 2.5-3D packaging, High-density I/O, Photonic packaging
Responsibilities
Develop and implement advanced packaging concepts for tiling large assemblies of ion trap, electrical, and optical chips; Lead cross-functional teams to develop packaging strategies for large-format ion trap chips; Generate packaging requirements for mechanical, thermal, electrical, and optical performance; Lead a team working with vendors to implement and validate packaging processes; Support all stages of ion trap development to ensure compatibility with packaging; Lead a team of packaging engineers to interface with broader Quantinuum team to ensure ion trap packaging meets system requirements; Champion engagements with 3rd parties to cultivate key partnerships, supplier relationships, and co-development opportunities
