Methodology Engineer (Silicon)
Core
Build and run automation for a single engineering methodology covering chip specification, design, verification, and signoff, connecting team procedures to make them cheap to follow.
Role type
Senior IC methodology engineer (silicon/verification tooling)
Builds
Linters, static checks, schema-driven records, dashboards, reports, and shared verification infrastructure for RTL, verification, and physical design teams.
Domain
Semiconductor silicon design and verification
Required skills
Python, Rust, CI systems (GitHub Actions), build systems (Bazel), chip development lifecycle (tapeout), linting, clock domain crossing checks, coverage analysis, ECOs, exception/waiver management, AI agent work review
Preferred skills
Formal verification, SystemVerilog Assertions, commercial lint/formal tools, DO-254/ISO 26262, data pipelines, AI coding agents, Bluespec
Technologies
Python, Rust, GitHub Actions, Bazel, SystemVerilog, Bluespec
Responsibilities
Design and maintain quality/verification tooling; generate signoff evidence and reporting dashboards; manage exceptions and waivers; develop shared verification infrastructure; apply methodology rules to AI-generated work; review escaped bugs and false alarms to improve processes
Seniority
Senior, hands-on IC
