Senior FPGA Design & Verification Engineer – Terwave
Core
Architect, design, implement, and verify FPGA-based modem and physical layer solutions for high-reliability space-based communications systems.
Role type
Senior IC FPGA Design & Verification Engineer
Builds
Digital signal processing and physical layer implementations for Terawave next-generation satellite modems
Domain
Aerospace / Satellite Communications / Digital Signal Processing
Deliverable
production ML models | product features
Required skills
RTL design (VHDL/Verilog/SystemVerilog), FPGA implementation of DSP/modem functions, verification methodologies (UVM, constrained-random), timing closure, SoC platform integration
Preferred skills
Digital communications theory (synchronization, equalization, carrier/timing recovery), embedded C/C++ development, hardware-in-the-loop (HIL) testing infrastructure
Technologies
Xilinx/AMD, Intel/Altera, UVM, SystemVerilog, VHDL, Verilog
Responsibilities
Architect and design FPGA implementations of modem and physical layer functions on a SoC FPGA platform; Translate communications system and DSP algorithm requirements into efficient, resource-optimized RTL; Develop and execute comprehensive verification strategies including self-checking testbenches and coverage-driven methodologies; Perform timing closure, resource optimization, and design implementation for high-performance FPGA and system-on-chip platforms; Support integration and hardware bring-up including lab testing, debug, and validation; Collaborate with DSP/communications engineers to co-design and optimize physical layer algorithms for fixed-point FPGA implementation; Contribute to design reviews, documentation, and design-for-test/design-for-reliability practices consistent with aerospace-grade development
Seniority
Senior, hands-on IC
