Principal Mixed Signal Architect
Core
Lead definition and development of high-performance mixed-signal subsystems for advanced communication and data-conversion SoCs, owning architecture, specifications, and cross-functional integration.
Role type
Principal Mixed-Signal Architect (Senior IC)
Builds
High-speed SerDes, ADCs, PLLs, VGAs, TIAs, and quantizers for spaceflight communication systems
Domain
Semiconductor / Aerospace / High-Speed Data Conversion
Deliverable
production ML models | product features
Required skills
Mixed-signal IC design, SerDes architecture (PAM4/NRZ), ADC design (SAR/Pipeline/Sigma-Delta), behavioral modeling (MATLAB/Simulink/SystemVerilog-AMS), calibration algorithms (FFE/DFE), RTL implementation, packaging integration, post-silicon validation, LDE management, advanced node design (FinFET)
Preferred skills
EM simulation, high-speed interface protocols (PCIe Gen5/Gen6, Ethernet), system modeling for communication/sensors, signal integrity analysis, lab bring-up
Technologies
Cadence Virtuoso, Spectre/HSPICE, AMS Designer, EMX, Ansys, MATLAB, Simulink, SystemVerilog-AMS, Oscilloscopes, BERTs
Responsibilities
Define top-level specifications and link budgets for SerDes and ADCs; develop behavioral models to validate system performance; lead circuit architecture and design for key analog/mixed-signal blocks; define calibration and adaptation algorithms implemented in RTL; partner with packaging teams on pinouts and isolation strategies; drive cross-functional architecture tradeoffs; lead post-silicon validation and debug using high-speed test equipment; provide technical leadership and mentorship
Seniority
Principal, hands-on IC with strategy & mentorship