Design Architect
Core
Lead building representative SoC sub-systems using partner systems (ARM) and Cadence design/verification collateral, porting them to Palladium/Protium hardware/software, and ensuring functional correctness.
Role type
Senior IC Hardware/Design Architect
Builds
ARM CSS based systems using Cadence AVIPS and IP (via careerplan.io/jobs/R56292-design-architect-at-cadence)
Domain
Semiconductor, SoC design, emulation hardware
Required skills
SoC design, verification, ARM bus protocols, performance analysis, RTL development, emulation experience
Preferred skills
SoC integration methodologies, verification automation, PCIe/CXL protocols
Technologies
System Verilog, Verilog, C/C++, SV-UVM, Cadence AVIPS, Palladium, Protium, ARM
Responsibilities
Build ARM CSS based systems using Cadence AVIPS and IP, port systems to Palladium/Protium hardware and software, ensure functional correctness, analyze and propose solutions to complex problems, make recommendations for performance improvements
Seniority
Senior, hands-on IC
