Lead Software Engineer - Low Power Verification
Core
Lead Software Engineer improving performance and usability of UPF debug features for multi-billion-gate low-power designs on Palladium and Protium emulation platforms.
Role type
Senior IC software engineer (low-power verification)
Builds
UPF debug tools, event logging, violation detection, and documentation for emulation/prototyping flows
Domain
Semiconductor EDA, low-power design verification, emulation platforms
Required skills
IEEE 1801 UPF, RTL languages (Verilog, SystemVerilog, VHDL), C++ code review, root-cause analysis from logs/waveforms, AI-assisted coding tools
Preferred skills
AI-assisted coding tools (Copilot, Claude, Cursor), technical writing, cross-team collaboration
Technologies
UPF, SystemVerilog, C++, Palladium, Protium, Parallel Partition Compiler, Modular Compiler
Responsibilities
Enhance UPF debug features across PPC and MC flows; Scale UPF event logging and violation detection; Rebuild UPF documentation with SystemVerilog examples; Develop AI-assisted UPF debug tools; Deploy UPF solutions across key flows; Consolidate UPF debug across platforms
Seniority
Senior, hands-on IC
