Principal Design Engineer
Core
Architect solutions for DDR controller features and design RTL in a highly configurable and automated environment.
Role type
Principal Design Engineering Architect (SoC/RTL)
Builds
DDR controllers and high-speed, low-power SoC features
Domain
Electronic Design Automation (EDA) / Semiconductor / Microelectronics
Deliverable
production ML models | product features
Required skills
Verilog RTL design, Metric Driven Verification (MDV), SoC architecture, Front-end design tools (LINT, Synthesis, CDC Analysis), Technical team leadership, High-speed circuit design, Low-power design, Design automation flows
Preferred skills
AMBA protocols (CHI, AXI, AHB, APB), SystemVerilog, ISO-9001/ISO-26262 quality processes
Technologies
Verilog, SystemVerilog, LINT, Synthesis tools, CDC Analysis tools, AMBA protocols
Responsibilities
Architect DDR controller solutions, Design RTL in automated environments, Collaborate with verification and PHY teams, Develop high-speed and low-power circuits, Refine development processes through automation
Seniority
Principal, hands-on IC with leadership
