Lead Design Engineer
Core
Design and verify high-speed, low-power SerDes transceivers for data-center, networking, AI, and high-performance computing applications.
Role type
Senior IC analog mixed-signal design engineer (SerDes)
Builds
Silicon-ready circuit architectures for high-speed transceivers
Domain
Semiconductor / Analog Mixed-Signal / High-Speed SerDes
Deliverable
production ML models | product features
Required skills
Analog CMOS design, noise analysis, jitter analysis, feedback control, signal integrity, data-converter fundamentals, transistor-level design, high-speed SerDes circuit design, Cadence Virtuoso, Spectre, ADE, parasitic extraction, mixed-signal verification flows
Preferred skills
PAM4/NRZ SerDes, advanced CMOS or FinFET technologies, Ethernet/PCIe/CXL standards, MATLAB, C, SystemVerilog, Verilog-A, Perl, Python, AI-assisted engineering tools, custom analog layout, lab characterization, mixed-signal IP tapeout
Technologies
Cadence Virtuoso, Spectre, Spectre RF, ADE, SystemVerilog, Verilog-A, MATLAB, C, Perl, Python
Responsibilities
Design and verify high-speed SerDes blocks (TX drivers, serializers, RX front ends, CTLEs, samplers, comparators, ADCs, DACs, PLLs, DLLs, clock networks, regulators, bias circuits, calibration loops); Translate link-level requirements into circuit specifications and optimize performance across PVT, mismatch, aging, and parasitics; Develop behavioral models and support mixed-signal and top-level verification; Collaborate with layout and signal-integrity teams on physical implementation and post-layout signoff; Support tapeout, silicon bring-up, characterization, debug, and production release; Document results and participate in technical design reviews
Seniority
Senior, hands-on IC