Firm ware Engineer II
Core
Design and implement firmware for high-speed SERDES physical layer IP, covering architecture, implementation, verification, and customer deployment.
Role type
Firmware Engineer II (Physical Layer IP)
Builds
High-speed SERDES IP for wireline communication
Domain
Semiconductor / High-speed serial-link protocols
Required skills
C/C++, Python, firmware architecture, firmware implementation, firmware verification, FuSa compliant firmware development, post-silicon testing, IP debugging, hot fixes, technical documentation
Preferred skills
wireline communication principles, digital signal processing, mixed signal circuit design, silicon validation process, digital verification environments
Technologies
C, C++, Python
Responsibilities
Collaborate with PHY digital and mixed signal architects on firmware functions and sequences; build system-level prototype control software for adaptation and equalization algorithms; implement firmware features and work with verification teams; develop test plans for FuSa compliance; support electrical and system characterization during post-silicon testing; debug IP issues during customer deployment and provide hot fixes; create and maintain firmware design and compliance documentation.
Seniority
Mid-level IC