High Speed PHY FW Engineer
Core
Developing physical IP firmware for industry-standard high-speed serial-link protocols (SERDES) to enable adaptation, equalization, and control algorithms in system-on-chip designs.
Role type
Firmware engineer for high-speed SERDES physical layer IP
Builds
Physical layer IP subsystems for smart sensors and smart city applications
Domain
Semiconductor IP, high-speed serial communication, electrical engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
C/C++ programming, Python, wireline communication principles, mixed-signal circuit design, digital signal processing, firmware architecture design, post-silicon debugging, system characterization
Preferred skills
None stated
Technologies
None explicitly listed beyond programming languages
Responsibilities
Develop firmware architecture and implement features for high-speed SERDES protocols; Debug firmware issues found in verification simulations; Support post-silicon testing and validation to identify and fix FW/HW functionality issues; Provide hot fixes for IP issues in the field; Support electrical and system characterization of the IP
Seniority
Mid-level IC engineer (T1/T2)