Lead Application Engineer – Digital Verification
Core
Lead technical evaluations and pre-sales engagements for Cadence's digital functional logic verification solutions, acting as a tech consultant to drive customer adoption.
Role type
Senior IC application engineer (digital verification)
Builds
Customer project evaluations and successful deployment of verification technologies
Domain
Semiconductor EDA / Digital Verification
Deliverable
client delivery
Required skills
UVM, SystemVerilog, Verilog, VHDL, SystemC, SVA, code coverage, functional coverage, hardware design/verification methodologies
Preferred skills
Cadence Verification IP, Jasper
Technologies
Cadence Verification IP, Jasper, UVM, SystemVerilog, Verilog, VHDL, SystemC, SVA
Responsibilities
Lead and support digital verification solutions for customer projects or pre-sales engagements; Identify, qualify, and scope opportunities with the sales team; Plan, execute, and manage key technical evaluations; Provide deep technical expertise to address complex customer issues; Deliver trainings, technical presentations, and product demonstrations; Summarize project activities and report to management.
Seniority
Senior, hands-on IC
