Design Engineering Architect
Core
Technical leadership of complex Intellectual Property (IP) including UCIe, Ethernet, HBM, and PCIe for high-tech markets.
Role type
Senior IC Design Engineering Architect
Builds
Industry-leading IP solutions for SoC development
Domain
Electronic design automation, microelectronics, semiconductor IP
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog RTL design, front-end design tools (LINT, synthesis, CDC/RDC), SoC architecture, technical team leadership, standards body participation
Preferred skills
Metric Driven Verification (MDV), UVM, industry standard protocols (AXI, CHI-C2C, CXS.B), quality processes (ISO-9001, ISO-26262)
Technologies
UCIe, Ethernet, HBM, PCIe, Verilog, SystemVerilog, LINT, UVM, AXI, CHI-C2C, CXS.B
Responsibilities
Define architecture and specifications for complex IP; lead RTL development from micro-architecture to sign-off; plan activities and milestones for digital development teams; lead cross-functional technical meetings; support customer pre-sales and post-sales meetings; develop and improve product execution processes; represent company in standards bodies and industry conferences
Seniority
Senior, hands-on IC with leadership
