Principal Design Engineer
Core
Lead subsystem and SoC-level design verification, defining methodology and mentoring engineers to ensure Si realization.
Role type
Principal Design Verification Engineer
Builds
Scalable verification environments and testbenches for complex SoC modules
Domain
Semiconductor / IC Design Verification (via careerplan.io/jobs/R54634-principal-design-engineer-at-cadence)
Deliverable
production ML models
Required skills
SystemVerilog UVM, SoC/Subsystem verification, Debugging, Verification architecture, ARM-based designs, AMBA protocols (AXI, ACE, APB, AHB), C-based test development, Mentoring
Preferred skills
Cadence tools, Formal Verification, Assembly language, Embedded C, USB/PCIe/Ethernet/DDR protocols, UART/I2C/SPI/JTAG
Technologies
SystemVerilog, UVM, C, ARM, AMBA, Cadence tools
Responsibilities
Define verification strategy and architecture, develop scalable UVM testbenches, execute and debug test cases for coverage goals, mentor junior engineers, collaborate with cross-functional teams
Seniority
Principal, hands-on IC with mentorship
