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Mixed Signal Systems and Verification Engineer II

2 Locations💼 Full-time🗓 2026-07-15 → 2026-07-31

Core

Develop and verify analog and mixed-signal behavioral models (RNM) in SystemVerilog to ensure accurate representation of analog schematics and design intent for high-performance computing and AI/ML applications.

Role type

Mixed-Signal Systems and Verification Engineer II

Builds

High-quality silicon designs including filters, ADC/DAC, VCO, A/DPLL, SerDes, LNA, and mixers

Domain

Semiconductor design, analog/mixed-signal verification, high-performance computing, AI/ML hardware

Deliverable

production ML models | product features

Required skills

SystemVerilog, real-number modeling (RNM), analog/mixed-signal verification concepts, testbench development, assertion-based verification, debugging across analog/digital domains, verification infrastructure maintenance, cross-functional collaboration

Preferred skills

Python/Perl scripting, low-power architecture experience, UVM methodologies, FPGA prototyping, industry standards (PCIe, USB, DDR), hardware acceleration platforms (Palladium, Protium), version control systems

Technologies

SystemVerilog, Verilog-AMS, wreal, UDN/UDT/UDR, Cadence Virtuoso Schematic Composer, Cadence ADE, Python, Perl, FPGA, Palladium, Protium, SVN, GIT

Responsibilities

Develop accurate simulation-efficient analog and mixed-signal behavioral models in SystemVerilog; Verify behavioral models against analog schematics and design intent; Integrate analog behavioral models with RTL environments; Verify analog and mixed-signal functionality against specifications using SystemVerilog testbenches, test scenarios, and assertions; Debug verification failures across analog, digital, and mixed-signal domains; Develop and maintain verification infrastructure including testbenches, environments, and scripts; Document modeling assumptions, verification methodology, and results for formal design and verification reviews; Collaborate cross-functionally with design, systems, and IP teams to understand constraints and ensure verification coverage

Seniority

Mid-level IC engineer (0-2+ years experience)

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