Lead Product Engineer: SoC Verification
Core
Lead Product Engineer driving the deployment and evolution of Cadence's Portable Stimulus (PSS) solution for complex SoC and system-level verification challenges.
Role type
Senior IC EDA product engineer (SoC verification methodology)
Builds
Portable Stimulus (PSS) deployment in production environments for semiconductor design teams
Domain
Semiconductor EDA / System-level verification
Deliverable
production ML models | product features
Required skills
SoC verification, SystemVerilog, UVM, constrained-random verification, system-level test generation, C/C++/Python scripting, debugging complex verification environments
Preferred skills
Portable Stimulus (PSS), Perspec tool, complex SoC subsystems (PCIe, DDR, networking, ARM), embedded software programming, emulation/virtual platforms, verification methodology development
Technologies
SystemVerilog, UVM, C, C++, Python, Portable Stimulus, Perspec
Responsibilities
Deploy Portable Stimulus methodologies in complex SoC programs; debug generation and solver issues involving constraints and execution ordering; investigate modeling challenges in large system-level PSS environments; collaborate with R&D to diagnose tool issues and influence new features; define and refine methodologies for scalable system-level verification; develop reference models and best practices for customers and field teams.
Seniority
Senior, hands-on IC
